For a given electrical apparatus, electronic components such as integrated circuits, and associated analog or logic circuitry, are typically situated and interconnected through conductive pathways situated on, or formed within, a main substrate board. Various configurations of such substrate boards can be used to form circuitry for countless electronic applications.
In implantable devices, such as pacemaker and defibrillator applications, it is important that the size of the main substrate board be as small as possible. One factor requiring a small substrate board is the limited physical dimensions of an associated product which makes use of the board. With such a product of limited dimensions, it becomes crucial not only to use miniature components, but also to configure and package the components in a particular layout so that use of the substrate-board surface area is optimized.
Modern cardiac pacemakers, and other implantable biomedical apparatus, have physical dimensions which are severely restricted. A reduction in pacemaker size translates into a smaller incision in the patient and a lighter pacemaker unit, in general. As implantable biomedical devices increase in complexity, it is a distinct challenge to prevent the size of these devices from increasing as a result.
The electronics in an implantable medical device typically include a microprocessor, Read Only Memory (ROM) or Random Access Memory (RAM) chips, and other associated active and passive components. These components are usually mounted and interconnected onto a microelectronic substrate or printed circuit board. The substrates used in these medical devices are primarily conventional thick film substrates and high temperature cofired ceramic substrates.
The electronics of pacemaker and other implantable medical devices typically contain components interconnected by "chip-and-wire" technology. Chip-and-wire may be defined as hybrid technology employing exclusively face-up-bonded chip devices interconnected to a substrate by "flying" wires, i.e., wirebonds.
Several U.S. patents have disclosed methods to increase the packing density of microelectronic circuit structures. For example, U.S. Pat. No. 3,302,067 issued to Jackson et al. discloses a method of placing circuit modules onto a mounting board. The mounting board is constructed with interconnecting pathways between each of the modules. The modules are constructed with active electronic components on one side and with electrical resistances deposited on an opposite side. The electrical resistances communicate with the active elements by wrap-around conducting pathways which are formed around the edges of the module. While these advances in component packing density are applicable to a number of different devices, many of them are not directly applicable to chip-and-wire technology.
With respect to chip-and-wire devices, several electronic packaging arrangements have been proposed which use multi-stacked integrated circuits connected to surrounding circuitry through bonding wires. For example, in U.S. Pat. No. 5,323,060 issued to Fogal et al., Fogal discloses stacking chips together to create a multi-chip module which is attached to an underlying substrate. The module is electrically connected to the substrate through bonding wires projecting from each individually-stacked chip to various locations on the mounting substrate. In U.S. Pat. No. 5,291,061 issued to Ball, a stacked die device is disclosed wherein pairs of die devices are attached together and their bond pads are alternately connected to a row of lead fingers.
A method of replacing an electronic component attached to a support substrate with bonding wires is shown in U.S. Pat. No. 4,567,643 issued to Droguet et al. In Droguet, a defective component is replaced by stacking an identical component on top of the defective component and then wire-bonding the new component to conducting tracks placed on the substrate. The defective component is then isolated from the conducting tracks by laser cutting away a portion of the track connected to the defective chip.
Along with performance and reliability, one of the ultimate design goals for cardiac pacemaker circuitry is reduced size. This means that a substrate containing the electronic circuitry must have a high component packing density. The mere stacking of integrated circuits by itself, however, is not necessarily an acceptable solution for reducing overall size.
Therefore, there is a need in the art for a vertically integrated semiconductor package for use in an implantable medical device which can significantly increase component packing density.